In addition, the diameter of the Ge/GeO x nanofilaments (or NWs) of approximately 40 nm is calculated using a new method under SET. The low-current operation of this RRAM device will make it useful in nanoscale nonvolatile memory applications. Methods Ge NWs

were grown by the VLS Epacadostat supplier technique using Ge powder as the starting material (purity of 99.999%). Silicon (Si) wafers with an ultrathin gold (Au) coating as a catalyst were used as substrates. The substrate was annealed at 600°C for 30 min in a vacuum chamber to form isolated Au nanoparticles (NPs), or commercial Au NPs were used as substrates to grow NWs. The typical diameter of the Au NPs was approximately 5 nm, which was determined by scanning electron microscopy (SEM) (Figure 1a). Ge powder was placed in an alumina selleck screening library boat and inserted in a horizontal tube furnace. The furnace was heated at 900°C for 30 min under argon with a flow rate of 10

sccm to grow NWs through the VLS technique. High-density Ge NWs with a diameter of approximately 100 nm and length of approximately 100 μm were observed by SEM (Figure 1b). The Ge NWs possessed a core-shell structure, ABT-737 order as shown in the transmission electron microscopy (TEM) image in Figure 1c. This suggests that the core region is Ge-rich, and the shell region is oxygen-rich, i.e., GeO x . It is expected that the GeO x layer will contain more defects than the Ge-rich core, which may be useful for resistive switching memory applications. The defects in the Ge/GeO x NWs were observed by both XPS and PL (Figures 2 and 3). PL measurements were obtained on a Triax 320 monochromator (Jobin Yvon, Edison, NJ, USA) and photomultiplier detector with an excitation wavelength of 325 nm. Figure 1 SEM and TEM images. SEM images of (a) Au nanoparticles and (b) Ge NWs on Si substrates. (c) TEM image of core-shell Ge/GeO x NWs. Figure 2 XPS spectra of Ge 3 d core-level

electrons of the Ge/GeO x NWs. Figure 3 PL and deconvoluted spectra. PL spectra of the Ge/GeO x NWs (a) measured at temperatures of 10 to 300 K and (b) deconvoluted spectra at 300 K. Defects in the Ge/GeO x NWs and resistive switching memory characteristics were also assessed by fabricating an IrO x /Al2O3/Ge NWs/SiO2/Si Olopatadine MOS structure, as shown in Figure 4a. MOS capacitors were fabricated using a shadow mask to pattern IrO x electrodes onto Al2O3 that was grown on dispersed Ge/GeO x NWs. The memory device consisted of three stacked layers: a top tunneling layer of Al2O3 (10 nm), a defect-rich Ge NW layer, and a thin tunneling layer of SiO2 (approximately 4 nm). After cleaning the Si wafer, an SiO2 layer was grown by annealing in a hot furnace as described above. The Ge/GeO x NWs were then dispersed on the SiO2/Si substrate. To deposit the TE of IrO x , a thin layer of Al2O3 was also deposited.